Retention register

As discussed earlier( post name : power gating ), When power gating is used, the system needs some form of state retention strategy to store it's internal state information.The best approach is to replace a standard register with a retention register when power gated domain is shut down. A retention register contains a shadow register that can save the register data during power down and restore it at power up.

Why only Retention register ?
Retention registers are special low leakage flip-flops used to hold the data of main register of the power gated block. These registers are always powered up. Power gating controller controls the retention mechanism such as when to save the current contents of the power gating block and when to restore it back.

Here one of the key architectural decision in power gating is how much state to retain during power down.Based on storage there are two types of retention.

1. Full state retention : Replacing all register present in the power gated block with retention register. (i.e Retaining the full state of the power gated block) during power down.
Advantage : Most robust, Verification is easy
Disadvantage : Area penalty

2. Partial state retention : Retaining some of the internal state of the block[Shallow state]is saved in the retention.But here the biggest challenge is to assure that all non retained register power up in legal, safe and variable states.

FIFOs, memories and counter are the best example where partial state retention is employed.

[Shallow state : Registers that directly control the logic of the design]
[Deep state : Registers that are used by the state machine which contain lager amount of data]

There are three types of retention.
1. Single save/restore pin retention latch (Slave latch being always on)
2. Single pin Balloon Latch.
3. Dual Pin Balloon Latch.
Figure shows a flop with retention cell(Dual pin baloon latch) along with the necessary control signals. SAVE and RESTORE.

SAVE is a control signal used to store the state of the register into retention latch.
RESTORE is a control signal used to restore the state of the register from the retention latch value.Restore operation is done irrespective of the clock.The retained value is forced into the slave latch.

When system wants turn off the power domain block following are steps to be followed in sequence :
1. Disable the clock .
2. Asserting SAVE signal before sending the turn off signal.
3. Disable the power(Vdd) to the block.

When system wants to turn on the power domain block,
1. Enable the power(Vdd) to the block.
2. Asserting RESTORE signal to retain the state of main register from retention latch.
3. Enable the clock.