Power Gating

From the previous post we have seen few techniques to reduce the dynamic power (Clock gating,Multi Vdd) as well as static power ( Multi Vt). But that is not enough since during standby mode the design continues to consume leakage power, Now let's move on to the most robust method 'Power gating technique' the most effective method to reduce the leakage current.

Power Gating or Power switch off technique is a mechanism to turn off the blocks temporarily when it is idle/based on the requirements to reduce the static power dissipation.The turn off time can also be called as "low power mode/inactive mode" .When the blocks are turned on once again,they are called as "active mode".The strategy behind power gating is to switch these two modes at the appropriate time to reduce the power while minimizing the impact on performance.

There are two types of architectural decisions with power gating:static power gating and dynamic power gating.

In static power gating ,we try to power gate a particular block in the design based on application and this block remains ON/OFF through out the normal operation of the chip until the chip is re- initialized or re-configured through external input signals or by setting certain configuration registers in the chip or during software re-initialization. This is a simpler approach that can be used based on the application requirements where on design,implementation and verification perspective there is only a need to check that the power gated block doesn't affect the functionality of the design.

For example, it could be switching of a peripheral interface of a CPU for a particular application.

In dynamic power gating ,the decision is made on the fly while the chip is running based on various parameters decided by the power control logic of the chip .The main goal of dynamic power gating is to reduce the leakage power of the chip by defining power domains and analyzing the data paths and modes of operation of the chip while it is running.The decision making of the power control for each power domain in the design is done either by software or hardware.

In a software based approach the driver software can schedule the power down/up operations.

For example ACPI introduced for PC's gives the controllability of power controlling decisions to the operating system.

The operating system is aware of new application, and it has the data to make power-management decision.Although ACPI targets desktops ans notebooks,it makes a good model to follow when developing a software based power management system for embedded systems. With ACPI, software automatically controls the power to peripherals, ans peripherals can also activate the processor.For example ,receiving an incoming call with a modem powers the processor from standby mode in time to capture the data.

In a hardware based approach either hardware timers are utilized or a dedicated power management controller is another option that maintains the control logic to control all the power domains.

(While in the whole blog when we refer to power gating , we are mainly referring to the dynamic power gating .)

The architecture and implementation of the power gating in a design ,includes certain trade-off's and challenges respectively, they are:

Architectural trade-offs involved with this technique :

1. Power gating affects design architecture.
2. It increases time delays as power gated modes have to be safely entered and exited.
3. The possible amount of leakage power saving in such low power mode and the energy dissipation to enter and exit such mode introduces some architectural trade-offs.
4. The time and energy cost to recover the lost data when the block is re entered to active
mode.

Implementation challenges involved with power gating are,

1. Adding sleep transistor/power switches to switch off the power supplies to the idle circuit.

1.The output of a power gated design may ramp off slowly , as a result these outputs spend significant amount of time at threshold voltage,thus causing large crowbar currents in the always power on block.Isolation strategy is required to overcome this.

2. Retention strategy is required for some power gated blocks, as it is required to store the internal state of block during power down and to store this state during power up.

3. A dedicated power management controller is required for shutting down the blocks in a proper sequence.

4. It also requires a system-level understanding to decide on the addition of power gates,isolation,retention in the design and when to control them.

5. Performing power aware verification of the design is a biggest challenge.

State retention and restoration required for those power gated designs that need to resume their operations on a wake-up event based on the states information.here are three methods for the state retention and restoration methods.

1. Application software that writes specified register and memory values to disk storage before shutting down power supplies. At wakeup,the software writes the saved states back into the design.

2. State-retention and -restoration method uses a design’s scan chains to shift out register states into an always powered memory before power-down and shift-in of the states at wake-up.

"Both the above methods usually take too long to read and write which consumes a lot of power."

3. Retention register and latches that contains a shadow register that can efficiently store and restore states during power down/up.