Multi Voltage(Vdd) Design:

As we have seen dynamic power is quadratic proportional to VDD, by lowering VDD , we can reduce the dynamic power significantly but at the cost of performance. So with this statement underlined, we can look at various parts of a particular design and analyze the critical and the non-critical paths and have a balance of low and high voltages based on the performance requirement of the path.

For example, take the USB card which we use to store data. It includes a processor block and its interface with the USB core . The processor block may require a high speed clock, while the USB core requires a low frequency clock in compliance with the protocol standards. So if we can give the low power that is required for the USB core to run, then we can drastically reduce the overall power consumed by the design.

Again within the design of the processor block , depending on it’s work load we can provide different voltages to the same block.

For example, RAM present in the processor block can be provided with Low voltage when there is no access to the contents of it’s memory and high voltage while performing reads and writes to the contents . So, it’s ultimatum on the architecture of the design to partition the design for different VDD’s based on the performance requirements and work load of the design.Thus based on the above examples , we can categorize the multi voltage strategies into

• Static voltage scaling: different fixed voltages are given to different blocks
• Multi level Voltage scaling: a block is switched between two or more voltages and fixed for a particular mode
• Dynamic voltage and Frequency scaling: based on the work load large number of voltage levels are switched dynamically
• Adaptive voltage scaling : same as above but here a control loop would be used that would adjust the voltage

Here while the blocks are partition for different VDD supplies, we need to insert Level Shifters between various voltage domains on the signals running between different blocks. These level shifters are buffers that translate the signal from one voltage swing to another(either Low to High or High to Low) .

Though this approach contributes for significant dynamic power reduction , it involves various complex decision of architectural strategies. Apart from this,
1. As different blocks in the design are at different voltages timing analysis becomes more complex.
2. Multi-voltage design require additional resources on the board(Regulators to provide additional supplies)
3. Should follow proper power up and power down sequencing.

As the design uses multiple power domains apart from the large power benefit , it has it's impact on the architecture, area penalty due to power grid and level shifter.performance degradation, signal integrity design and verification.

We will discuss on the importance of level shifter in the next few posts(during the discussion of power gating technique).