Power gated switches.(sleep transistor)

A sleep transistor is reffered to either PMOS or NMOS high Vth transistor that connects power to the power domain from the permanent power supply which is commonly called "virtual power supply ".
The sleep transistors are controlled by a power management unit to switch on/off power supply to the circuit.The PMOS sleep transistor is named as "Header switch" and the NMOS sleep transistor is named as "Footer switch".

Header switches turn off VDD and keep VSS on. As a result, the output of a power gated block collapse towards the ground(output capacitor discharges towards the ground) when the switch is turned off.It allows a simple design of a pull-down transistor(PMOS) to isolate power-off cells and clamp output signals in “0”.

The footer switch is used to control VSS supply. As a result the output of power gated block charge towards the supply voltage(vdd) when the switch is turned off. Designs become more sensitive to ground noise on the virtual ground (VIRTUAL_VSS) coupled through the footer switch. The isolation on “0 state becomes complex due to loss of the virtual ground in sleep mode and necessity of bypassing footer switch to reach permanent VSS.

Footer and Header sleep transistor with isolation cell.

The key issues affecting while taking the desicion are "Area, cost,IR drop constraints". The below are the few advantage/disadvantage with the Header and footer switches :
1. Footer switch occupy less silicon area relative to Header switch.
2. PMOS transistor is less leaky than NMOS transistor of a same size.
3. PMOS has lower drive current than NMOS of a same size.