Introduction to UPF

Unified Power Format(UPF) is a unique wide power format standard developed by Accellera that helps to deploy a power aware design information that cannot be specified in HDL's. In simple terms it helps us to tie the HDL's logic specification to the constrained power implementation with common semantics that can be deployed for verification as well as implementation.Thus what is designed and written in UPF is what is verified and what is implemented.

The above figure indicates the various steps during the process flow , where the UPF files become part of the design source for that stage .UPF along with RTL in complete describes the intent of the designer , which is later passed to the Synthesis tool that reads the RTL/UPF design input files and produces a netlist that might also produce a new UPF fileset which, combined with the netlist, represents a further refined version of same design. This netlist along with the redefined UPF or unaltered UPF goes as an input to a UPF-aware logic equivalence checker that performs equivalence checks including the UPF commands and later the place and route tool that reads both the netlist and the UPF files and produces outputs along with an output UPF file.

Apart from this the Simulator provides simulation models which accurately models the isolation,retention ,power switch,level shifter behavior based on the power intent of the design specified through RTL/UPF.This helps inthe functional verification of the power intent of the design along with the logical functioanlity.

UPF Power Intent Definition: The UPF definition includes definition of power distribution architecture that includes power domains ,supply rails and switches;power strategies that include power state tables and usage of special cells like isolation,retention,level shifter and power switches .
For example,

In the above figure, UPF extends the existing RTL with power-related functionality and bridges the gap between the power controller and the RTL extensions, making it easier to do functional verification at the RTL without embedding the power-related features into the golden RTL.

Looking at some basic definitions:

Power domain : A group of design elements that share a primary supply.

Supply port : Supply port that originates a supply state and voltage value.

Supply net : Propagates a supply state from one supply net to another.

Scope: A particular design element in the logic hierarchy.

Power state : The state of a supply net or supply port i.e ON/OFF.

Regulator : A design element that takes a set of input supply nets and provides the source for a set of output supply nets. The output voltage is a function of combining the input voltage and the logical state of any control signals.

Switch: A design element that conditionally connects one or more input supply nets to a single output supply net according to the logical state of one or more control inputs.

Now, in our next subsequent blogs we can look into the modelling of different cells using UPF commands.