Isolation Cell

As discussed earlier , with a header switch fabric, the output of the power domain block discharges towards Vss, while in case of a footer switch fabric, the output charges towards Vdd when the switch is turned off. Here there is no guarantee that the power gated output will fully discharge to ground or charge to the supply, which results in a floating output(transistors spend more in threshold results in a crowbar current) which in turn affects the behavior of the power-on block.In order to overcome this, an isolation strategy is required at the output of the power gated block.

One of the isolation strategy to combat the above effects is an isolation cell that isolates the power gated block from the power on block by clamping the output of the power gated block to a fixed value either logic '1' or logic '0' depending on the isolation control signal given by the power controller block.

Why only isolation cells ?
Isolation cells in the library are designed so that they do not experience the crowbar current when input signal floats, as long as the isolation control input is off.They are always powered on during the power down mode.

There are various combinations of gates and transistors for achieving the property of isolation.
1. AND gate function clamps the output at '0'
2. OR gate function clamps the output at '1'
3. PULL up(pmos) transistor clamps the output at '1'
4. PULL down(nmos) transitor clamps the output at '0' when it receives the isolation control signal from the power gated controller.

While the transistor approach introduces multiple drivers on the power gated net(Net becomes a shared channel) a careful sequencing is required in order to avoid this contention where testability becomes very difficult. The advantage is , it occupies less silicon area and less timing cost as compared to a gate-style isolation cell.