Implementation of power gating in a design

The key elements required while implementing the power gating technique in the design are
1. Power gated switches.
2. Isolation cells.
3. Retention Cells.
4. Level shifter.

The entire design is divided into a number of power gated functional blocks(A collection of design elements which share the common supply), always on functional block,Power switching Fabric and Power gating controller.

Power switching network : Unlike always_on block the power gated block receives its power through power switching network.This network switches either Vdd or Vss to the power gated block.The switching fabric typically consist of large number cmos switches distributed or within the power gated block.

There are two approaches for controlling the power to the power gated domain.

1. Fine grain power gating: Fine-grain power gating encapsulates the switching transistor as a part of the standard cell logic. Here the primary burden of adding switching transistors is left with the library IP provider or standard cell designer. This means that it is possible to use a traditional design flow to deploy fine grain power gating but significantly increases the silicon area..
An example of a fine-grain power gated shown below, where we can observe power switch is connected directly to the standard cell.In order to keep the area overhead to a minimum, fine-grained power gates are implemented as footer switches to ground as NMOS transistor.

The disadvantage of the fine-grain sleep transistor is implementation adds a sleep transistor to every cell that results in significant area increase. Also, it is not able to use the normal standard cells provided by library vendors and ASIC
foundries. Another issue is that the cells become more sensitive to PVT variations, because the built-in sleep transistor is subject to PVT variation which results in added IR-drop variation inthe cell and hence performance variation.

2. Coarse grain power gating : In coarse-grain power gating, the power-gating transistor is a part of the power distribution network rather than the standard cell. One sleep transistor cell is used to turn on and off a set of standard cells(power domain function block).

The coarse-grained approach requires less area than fine-grain power gating due to the lower number of sleep transistors and less routing of enable signals for power gating. Fewer sleep transistors result in better leakage control.
The disadvantage is it might take several clock cycles to power up a larger block of logic cells.

An example of coarse grain power gating is shown below where we can see single power switch transistor is connected to the power gated logic.

The advantage of this approach is less sensitive to PVT variation and introduces less IR-drop variations than the “fine-grain” implementations. Also, the area overhead is significantly smaller as compared to fine-grain.

There are two ways of implementing a coarse-grain structure:

2.a Ring-based Network: The power switches are placed around the perimeter of the power gated block that is being switched-off as a ring.
In the ring style implementation, a virtual power ring is added to surround each power domain. The sleep transistors are placed between permanent power ring and virtual power rings to control power supply to each power domain, as shown in Fig,

It has small impact on placement and routing. However, it could result in more IR-drop at center of the design due to thelimited drive of the sleep transistors distance from the center.

2.b Grid/Column-based Network: The power gates are distributed throughout the power gated region.

In the grid style sleep transistor implementation, the sleep transistors are placed close to power grid to connect permanent power network and virtual power networks, as shown in the above Fig.

The advantages of the grid style implementation are the better IR-drop management because each sleep transistor drives local cells.

The drawback of the implementation is its impact on routing and physical synthesis, because the sleep transistors are distributed in the design area.

Here the key challenge involved with the switching fabric is to limit the in-rush current(causes voltage spikes on the supply) when the power is reconnected to power gated block to avoid the excessive IR drop in the power network.This drop in turn increases the delay in the network.It can corrupt the function as well as retention register in the power gated blocks when power is reconnected if in rush current is not controlled.