Power gated controller.

In our previous discussion, we have seen that control signals are required for each power cell in a proper sequence to achieve power gated technique in the design.

During the architecture phase of the project,
Designer will make the decision on which block to shut-down and when and how long this has to be shut-down, is isolation required or not,is retention required or not if required how much state to retain during power down.

Godwin in his blog, well suggests to have a separate power gated controller block for each power domain that takes inputs from the main power control logic and generates the power down signals in the desired sequence. Few control signals required to perform the above task are,
1. Control Signal for the Power Switch (PWR_EN)
2. Control Signal for the Isolation Cell Enable (ISO_EN)
3. Control Signal for the retention flops (SAVE and RESTORE)

All the above signals need to be generated in the right order to avoid the malfunction of the circuit.
One of the sequence to follow,
To power-down the block :
1. Disable the clock
2. Generate SAVE : This will indicate that the contents of the main register in the power gated block moved into retention latch.
3. Generate ISO_EN: This will enable isolation cells to be active and clamp the output of the power gated block to either '1' or '0'.
4. Since all the basic elements are informed of the shut-down operation, now generate PWR_EN, to turn off the power rails, that control specific blocks.

To power-up the block :
1. Generate PWR_EN, to turn on the power rails, that control specific blocks.
2. Disable ISO_EN : This will disable isolation cells.Once disabled, the output of the power gated block is connected to the next power-on block.
3.Generate RESTORE : This will indicate that the the main register in the power gated block restore the data saved in retention latch.
4. Enable the clock.