Multi Threshold (Vt) Design

As we have seen earlier, subthreshold leakage depends exponentially on Vt; while the delay has a much weaker dependence on Vt.Thus libraries with multiple Vt has become a common way of reducing leakage current and balancing the timing constraint of the design.

Silicon foundaries provide multiple threshold libraries at the same process node :

1. Low Vt : This produces least cell count and least dynamic power,But produce highest leakage power compared to other Vt cells. It runs faster. Good for a design with very tight timing constraints.

2. Standard(Nominal) Vt : A standard Vth cell maintains it's characteristics for leakage and delay between low Vt and High Vt cells.

3. High Vt cells :Produce least leakage power consumption but has high cell count and dynamic power. This methodology is good for leakage power critical design at the expense of speed of the device.It runs slow.




Thus it's the implementation tool which has to use the various cells in the library and create an implementation that will meet the timing constraints while reducing the leakage current as much as possible.Use lower threshold gates on critical path while higher threshold gates off the critical path.

The decision making process of deciding on the different Vt cells renders simplified and efficient by considering the trade-offs early in the synthesis process. Usually as there is a minimum performance to be met before optimizing the power,the design is first synthesized for high performance by using a low threshold voltage library at first pass and then later the decision making is done in locating all those areas in the design which doesn't require low Vt cells and then they are swapped with the High Vt cells.

However, there could also be some applications where power is the main goal then the low leakage library is targetted first which is later swapped by higher performing ,higher leakage equivalents in speed critical areas.

Multiple voltage thresholds can reduce power consumption with a little impact on Timing, area and place and route.