Level Shifters

As discussed , as the design incorporates a mix of voltages , there is a need for a voltage translation logic that takes care of the interfaces between different voltage domains.

Practically, if looked at a signal in a 5v domain if driven by a signal from a 1v domain,it is a cause of concern as a 1v swing would not be reaching even the threshold value of the 5v swing.But,presently with the shrinking technology most of the chips have their voltages around 1v in the view of reducing dynamic power.
Then here there could be a question like, how could a signal from a 0.9v domain driving a 1v domain could pose any problem. Here the problem comes from the fact that such a 0.9v signal could make both the transistors ON thus resulting in a crowbar current(Both pmos and nmos are ON when the voltage lies between Vtn and Vdd+Vtp) .Apart from this there could also be certain timing closure problems for each voltage domain when the required voltage swings are not met.Thus it's here the solution of level shifters mitigates the problem.

The purpose of the level shifter is to convert the signal voltage to the correct voltage of the receiving domain.There are two cases :

Shifting the voltage down: This is easier than shifting the voltage high.A simple level shifter circuit of H2L type could be a simple inverter or buffer that is powered by the lower voltage domain.

Shifting the voltage high: This is complex because of the low strengths of the driving signal.The circuit is complex with usage of two power supplies from both the domains.Thus there is also a requirment of careful placement of these cells to minimize the area.

In applications where there is a mix of power gating and Multiple VDD strategies in the design there are special cells called Enable Level Shifters(ELS), that combine the isolation logic along with the level shifter fucntionality.