Level Shifter(upf)

Level shifter translates from one voltage swing to another.UPF provides set_level_shifter construct to achieve this.

Syntax :
set_level_shifter level_shifter_name
-domain domain_name
[-elements list]
[-applies_to ]
[-threshold value]
[-rule ]
[-location ][-no_shift]

Example :


UPF code
set_level_shifter my_ls
-domain PDgreen
-rule low_to_high
-location self
-applies_to outputs
-threshold 0.02

Here, the signal going from lower voltage (p5 or p6)to higher voltage(p7) get a low_to_high level shifter when the voltage difference exceeds that specified threshold (0.02).

In our next blog we will discuss more on how UPF is used to define power distribution network (Defining power domain,supply port,supply net) and power states tables with examples.

Retention(upf)

UPF provides set_retention and set_retention_control constructs to add retention strategy in the design.

Syntax :

set_retention retention_name
-domain domain_name
[-retention_power_net net_name
-retention_ground_net net_name]
[-elements list]

set_retention_control retention_name
-domain domain_name
-save_signal {{net_name }}
-restore_signal {{net_name }}
[-assert_r_mutex {{net_name }}]*
[-assert_s_mutex {{net_name }}]*
[-assert_rs_mutex {{net_name }}]*


A simulation model for retention cell :

reg save_q; // shadow register
always @( posedge save_1 )
begin // save process
save_q <= q;
end

always @( negedge restore_1 )
begin // restore process
q <= save_q;
end

Example :

set_retention ret3
–domain PDgreen
–retention_power_net Vbu ----> Back up vdd
–elements { u37 } ----> Name

set_retention_control ret3
–domain PDgreen
–save_signal s ----> SAVE
–restore_signal r ----> RESTORE

Isolation(upf)

Isolation is used to clamp the output value of power gated block to fixed value during power-down state. UPF provides set_isolation and set_isolation_control constructs to add isolation strategy in the design.

Syntax for isolation cell :

set_isolation isolation_name
-domain domain_name
<-isolation_power_net net_name -isolation_ground_net net_name-isolation_power_net net_name -isolation_ground_net net_name
-no_isolation>
-clamp_value <01latchz>
-applies_to
[latch : The value of the non-isolated port when the isolation signal becomes active.]

Syntax to specify the control signals for isolation strategy.

set_isolation_control isolation_name
-domain domain_name
-isolation_signal signal_name
[-isolation_sense <highlow> ]
[-location ]

[location : Specifies the location for isolation cell to be placed in the logic hierarchy]
A simulation model for isolation cell :

always @( iso_enable, non_isolated )
begin
if (iso_enable == isolation_sense )
isolated = clamp_value;
else
isolated = non-isolated; // Output of the power gated block.
end

Every time the control signal changes value, the new value is compared with its corresponding isolation sense value.If the control signal is the same as the sense value, the specified clamp value is driven as the isolated signal; otherwise, the non-isolated signal propagates as the isolated value.If power supply to the corresponding isolation elements is turned off or the enable signal is X or Z, the isolated signal is driven to X.

Example :

set_isolation iso3
–domain PDgreen
–isolation_power_net Vbu ----> Back up power net
–clamp_value 0 ----> Clamp isolation output to 0
–applies_to outputs ----> Isolates the outputs

set_isolation_control iso3
–domain PDgreen
–isolation_signal CPU_iso ----> Isolation enable
–isolation_sense low
–location self ----> Iso cell desired location

When isolation signal CPU_iso goes low, isolation cell becomes active clamps the outputs of iso3 to 0 else isolation cell became inactive i.e it propagates non-isolated value as isolated value.

Power switch(upf)

An element that connects power to the power domain supply from the permanent power supply depending the control signal.

Syntax :

create_power_switch switch_name
-domain domain_name
-output_supply_port {port_name supply_net_name}
{-input_supply_port {port_name supply_net_name}}*
{-control_port {port_name net_name}}*
{-on_state {state_name input_supply_port {boolean_function}}}*


Example :

UPF Code :

create_power_switch sw_controller

-domain PD_CONTROLLER

-input_supply_port [list VDDT VDDL_o]-->Input supply

-output_supply_port [list VDDc VDDL_2]-->output supply

-control_port [list EN PSE]-->Switch enable

-on_state [list on_state VDDT EN]--> ON state

-off_state [list off_state {!EN}}-->OFF state

The switch is ON based on the ON state of the control signal (PSE) , and drives the value specified on the input supply port (VDDL_o) on the output supply port (VDDL_2).

The switch is OFF based on the OFF state of the control signal (PSE) , and then OFF state is driven on the output supply port (VDDL_2).

Introduction to UPF

Unified Power Format(UPF) is a unique wide power format standard developed by Accellera that helps to deploy a power aware design information that cannot be specified in HDL's. In simple terms it helps us to tie the HDL's logic specification to the constrained power implementation with common semantics that can be deployed for verification as well as implementation.Thus what is designed and written in UPF is what is verified and what is implemented.

The above figure indicates the various steps during the process flow , where the UPF files become part of the design source for that stage .UPF along with RTL in complete describes the intent of the designer , which is later passed to the Synthesis tool that reads the RTL/UPF design input files and produces a netlist that might also produce a new UPF fileset which, combined with the netlist, represents a further refined version of same design. This netlist along with the redefined UPF or unaltered UPF goes as an input to a UPF-aware logic equivalence checker that performs equivalence checks including the UPF commands and later the place and route tool that reads both the netlist and the UPF files and produces outputs along with an output UPF file.

Apart from this the Simulator provides simulation models which accurately models the isolation,retention ,power switch,level shifter behavior based on the power intent of the design specified through RTL/UPF.This helps inthe functional verification of the power intent of the design along with the logical functioanlity.

UPF Power Intent Definition: The UPF definition includes definition of power distribution architecture that includes power domains ,supply rails and switches;power strategies that include power state tables and usage of special cells like isolation,retention,level shifter and power switches .
For example,

In the above figure, UPF extends the existing RTL with power-related functionality and bridges the gap between the power controller and the RTL extensions, making it easier to do functional verification at the RTL without embedding the power-related features into the golden RTL.

Looking at some basic definitions:

Power domain : A group of design elements that share a primary supply.

Supply port : Supply port that originates a supply state and voltage value.

Supply net : Propagates a supply state from one supply net to another.

Scope: A particular design element in the logic hierarchy.

Power state : The state of a supply net or supply port i.e ON/OFF.

Regulator : A design element that takes a set of input supply nets and provides the source for a set of output supply nets. The output voltage is a function of combining the input voltage and the logical state of any control signals.

Switch: A design element that conditionally connects one or more input supply nets to a single output supply net according to the logical state of one or more control inputs.

Now, in our next subsequent blogs we can look into the modelling of different cells using UPF commands.

Other Methods of Power reduction

Having looked at the various methods and techniques that can be applied at the architectural level of the design and the verification challenges thus involved and before moving ahead with the introduction to UPF which makes it easy ,there are other areas like Low power Logic synthesis, software based power reduction.There could be more areas apart from this,we would update the blog as and when we understand them.


Low Power Logic Synthesis:This includes state assignment,retiming,logic minimization and technology remapping for low power in the design.State encoding has formed one of the crucial areas where it not only accounts for area minimization but also for power reduction.Based on a couple of research studies conducted, reduction of switching activity of the input state lines of a next state logic during state assignment formed one of the key areas for power reduction and Minimum Weighted hamming Distance encoding like gray coding forms one of the solutions to reduce that switching activity and thus the power.Apart from this there had been proposals of using T-Flip Flops in the design because it results in natural clock gating and would also result in reduced next state logic complexity.Sometimes a combination of T-Flip Flop and D- Flip Flop had also turned out to be one of the approaches to use , where the T-Flip Flop is usef on high switching activity bit lines thus reducing the combinatorial logic realization and thus the power consumtption;and D-flip flop on low switching activity bit lines for it's easier to implement and also simulatneously reduces the power .

Apart from the mentioned above ,low power retiming is also one approach to reduce the dynamic power consumption which is performed by the synthesis tool which is based on the calculation of the power reduction by relocating the registers while having a calculation of the glitches thus produced due to the relocation of register and the switching activity of the sequential circuit.


Software based Power Reduction Method: Take an example of a CPU in our PC.While we had been concentrating on various techniques to reduce the power on the CPU,it's the software that executes on the CPU that determines its power consumption.

A simple example for an inefficient software could be something that includes "busy wait loops".There could be an application like SpreadSheet or a Word document that waits for the user inputs,and during those times the spreadsheet or the word document would be simply recalculating the values thus using the CPU in high power activity, while it's expected to be in "inactive" state until the user types in the value.This inefficient behaviour is accounted by the "busy wait loops" executed by the software on the CPU.Thus power-aware software have come into the industry that understands the hadware activity and acts accordingly in mitigating the power consumtption of the system.

Verification challenges involved with low power design

With the introduction of the complex on-chip power management techniques , there is an increase in the possibility of a design error that can be destructive if the false current paths are not detected and properly controlled and thus imposes a challenge in the verification of the design.On chip power management is fundamentally an analog/mixed signal problem , demanding analysis of both analog and digital circuit behavior.

For every power management technique there is a need for both dynamic verification and static verification.While dynamic verification is a test vector based verification to validate the functionality of the design;static verification is a vector less approach which performs structural and architectural checks of the design.

Verify Multi Voltage Design:

Prior to MV design technique, every design had two power states ON state and an OFF state , as the design works on single Supply voltage. This made the verification easy as the whole design understands the boolean logic '0' and '1' for the same voltage level.

With the MV design technique included in the design, apart from the ON/OFF states,there are more n different combination of power states included based on the different voltage supplies used inside the design , thus increasing the number of power states and their transitions.This also defines different voltage levels for '0' and '1' in different blocks of the design. Thus while we verify the signal interface between different voltage domain blocks,it's not the boolean value validation but the voltage levels of the signals that needs to be validated. Level shifters should be taken into account during the logic conversion of signals from one voltage domain to another.

Apart from this there is a need for a Voltage aware verification to verify the MV islands in the design.
1.

For example, In the above figure we can see there are three voltage domains with different power modes/states that is defined by the voltage at which each domain is working.Here we need to ensure that the Memory content is not lost when the supply rail falls below the standby voltage for that particular voltage domain.

2.In case of DVFS(Dynamic Voltage Frequency scaling) , since voltages are changed during run time,we need to check that the voltage ramp times are carefully controlled to avoid voltage overshoot or undershoot which can lead to the malfunctioning of the system.

3.Apart from the mentioned scenarios , there is also a need to perform static verification checks to validate
a. Level shifters by providing a separate constraint for each supply voltage level
b. If the power switch control signals are generated from appropriate domains.
c. Clock tree(to verify the clock swings from one voltage domain to another voltage domain)
d. Reset signals for the design
e. Finally timing checks for a block operating at different voltages(different voltages can
demand the same block to meet different performance objectives) by performing static
timing analysis.


Power Gating:

Unlike multi-VDD , power gating demands a Power-Aware verification as in a power gating technique various blocks in the design are completely shut-off /on based on the control signals coming from Power controller.For all those blocks with the power gated logic implemented, we need to verify two major states for that block in the design the Power Up and Power Down state, which cumulates into a set of power states for the design to operate.

Now, Let's look at the major challenges that come along with power-gating :

1.Power states: To verify the functionality of the design in every power state.;

2.Power State transitions: To verify the functionality of each block in the design while the design transits from one power state to another to ensure all legal state entry and exist.

3.Valid Power sequences: The power sequence is mainly to ensure the right voltage switches are ON for a particular block in the design.Here we need to validate
a. All power domains are completely powered up before issuing reset.
b. Main control unit of the design doesn't power up until entire chip is powered up.

For example , in the below figure we can see three power domains with its respective power table intent showing the power states and their transitions.




4. To ensure that the powered down block does not evaluate the events of the input transitions to the block .This can be evaluated by checking that there are no transitions on the inputs of the always-on block coming from the power gated block.

5. The pass through wires of a powered down logic are not affected, i.e. there can be a set of wires routed through the powered down logic , the logic of these wires should remain unaffected.

6. On powering up the power gated blocks,need to verify that the logic behavior in the block is enabled for evaluation, i.e. combinatorial logic and latches are re-evaluated,continuous assignments are re-evaluated and edge triggered logic of the flops are evaluated on next active edge.

7. To verify the power up sequence that powers up and down the various blocks in the design and the acknowledgment thus received.

8. To verify that the power gated block doesn't resume it's operation until the switching fabric is completely powered up.

9. If same power rail is used for external switching and internal switching , then need to verify the always-on logic which might remain off during external switching.

10. To detect the wastage of power in the design:
For example toggling of clock when power domain is in OFF state.

11 .There's also a need to emulate the IR drops and analyze the circuit behavior for the same.

Verifying Retention :

1. There is a need to verify that proper timing of the control signal (SAVE) is provided for the retention registers to save the values of those registers required before powering down.Improper timing can lead to corrupted data storage.

2. There is a need to verify that the proper timing of control signals(RESTORE) are provided to the retention registers to restore the values of those registers required on power up.Improper timing would end up in trying to restore the values before the registers intended are not powered up.Thus malfunctioning of the circuit.

Apart from this neither clock nor reset should be provided to the power gated block while the retention registers are saving/restoring the information.

3. If the power gated block is employing partial retention, functional testing is required to ensure that there are no illegal combination states that might cause deadlock.
For example:In order to allow the powered down block to restart correctly , the non-retention registers are fed with X values.So there is a need to verify that the non-retention registers are corrupted during power down and remain corrupted even after power up until the controlling logic is re-evaluated.Here there is also a need to verify that on power up of the block, the X values in the non-retention registers doesn't propagate and affect the function of the circuit.

4.Need to verify the X's are not propagated once the power gated block is restarted.

5. Retention registers in a block are properly connected and remain always-on and are not effected by either power-up or power-down of the respective block.Improper power supply connection will lead to loss of data storage.

Verifying Isolation :

1. To verify the unintentional propagation of high impedance states from power gated block to the always-on block.This mainly comes under static verification in structural checks to look for missing isolation cells in the design

2. Isolation logic of the particular power domain is also properly connected to the isolation power and ground and remains untouched by the power gated block.Improper power supply connection will lead to transmission of undesired signals.

3. Need to verify multiple net condition for the outputs of isolation cells while pull-up and pull-down clamps are used as isolation cells.

4. To verify that the domain of the control signals that are provided to the isolation cell are buffered by the always-on buffers.

5. Verify stuck at '1' and stuck at '0' at the output of the isolation cell.

Assertions should be provided at the power gating controller ports to ensure that the required switching technology, the above mentioned functionality and coverage are met.The power gating control signals should be controllable while testing .

Having said thus, all these and most of them form part of the functional check of the design where the functionality of the design has to be checked against various control signals generated by a power controller unit in the design,power switches,various domain interfaces that include the isolation cells,retention registers,ELS and level shifters.But then, all these do no exist in the RTL(and thus the control signals remain floating) and later during synthesis, the tool smartly adds these cells .

In order to emulate the behavior of those cells for simulation, one of the possible solution is PLI's. But then, the major concern here is there should be two RTL's , one with PLIs to simulate the behavior and one without PLIs for synthesis.

In order to combat this huge burden that comes with the complex designs and more of power saving strategies ahead,UPF standard has been introduced that helps in capturing the power intent of a design that goes through the entire flow of a design for both verification tool and the Implementation tool.