Scope of the problem

The power consumption of a SOC design has two components: dynamic power and static power .
i.e Ptotal = Pstatic + Pdynamic;


Dynamic power is the power consumed when the device is active ,i.e. when the signals are changing their values.Static power is the power consumed when the device is powered up , but no signals are changing values and it's accounted mainly due to the leakage esp in CMOS devices.

Dynamic power (Iswitch):
It mainly has two components ; the first arises from the momentary short circuit currents called crowbar currents that flow from power to ground when the transistor stack switches it's state i.e. while the transistor's inputs change from low to high or from high to low , the p-channel and n-channel transistors are both for an instant "on" in their linear regions.

The second component is the capacitive power - the power required to charge and discharge the output capacitance on a gate

Pdyn = Load capacitance(C) * square of the supply voltage(Vdd) * frequency(f)

If the ramp time of the input signal can be made short, then the dynamic power is dominated mainly by the capacitive power
Thus if observed, due to the quadratic dependency of the power on the supply voltage , reducing the supply voltage would be the best option.But, by lowering the supply voltage we are also trying to lower the transistor output currents,lengthening the signal delays and thus degrading the performance.So in order to balance this effect the threshold voltage levels are also lowered along with the supply voltage .

Static power (Ileak):
Static power has four main sources of Leakage Currents;
Sub-Threshold leakage Current : The current that flow from drain to source when operating in weak inversion region
Gate leakage Current : The current that flows due to gate oxide tunneling and hot carrier injection
Gate Induced Drain Leakage : The current that flows from drain to substrate due to high field effect in the drain
Reverse Bias Leakage : The current due to minority carrier generation and drift in depletion regions

Among the four components, Sub-Threshold leakage forms the dominant component due to it's negative exponential dependency on threshold voltage ; i.e. as mentioned before to meet the performance and reduce dynamic power if Vt is reduced then Sub-threshold leakage increases exponentially with Vt.This trade off becomes a main point of concern while deciding the low power strategies. One of the methods proposed for decreasing the leakage current is using reverse-body bias (RBB) to increase the threshold voltage of transistors in the STANDBY state

With the shrinking technology, gate-oxide is so thin, and the gate leakage current is growing exponentially,and the use of high -K dielectric material forms the only effective way to reduce this leakage. As we move ahead towards 65nm and 45nm ; the dynamic power equals to leakage current equals to gate leakage current.
According to one of the IRTS reports,at the 65-nm node, dynamic-power density and leakage power would increase by 1.43 and 2.5 times, respectively. At the 45-nm node, the ITRS predicts, dynamic-power and leakage-power density will increase to two and 6.5 times, respectively. In reality, designs in high-speed 65-nm processes lose as much as half their power to leakage. Many in the industry believe that, by the 45-nm node, ICs will lose as much as 60% of their power to leakage.