If we look at the process flow, the biggest opportunities for power reduction exist in pre-synthesis at the higher levels of abstraction. Since 80% or more of chip power is determined at the register transfer level (RTL) or at the architectural level, full chip analysis before synthesis can help in isolating architectural power problems that may be easily solved with RTL modifications.
Once the design is synthesized, there is much less opportunity to reduce power consumption. At the same time, accurate verification is critical at this stage to ensure that the design meets its power consumption specification.
In the recent days of advancements in technology _power consumption_ along with performance became the new metric for competitiveness in high-end SoC markets.In order to deal with power management the whole electronics community is employing various techniques for power reduction.
Managing the power early in Architectural exploration :
MAS(Micro Architecutral Specification) of RTL is the prime level to calculate the gate count in turn to determine the total power consumption of the chip.Designer should tackle power at one or more abstraction level depending on their needs and to go for refining the architecture by using additional low-power design techniques. ( Making more appropriate micro-architecture to create low power design) .
In simple words to achieve low-power targets, SoC designers must take a top-down approach beginning at the architectural level, continuing through RTL analysis and optimization, to power sign off.
One should analyze the effect on performance and the silicon area before evaluating the low power management technique during the architectural level. There are various power reduction methods that have been in use for some time and which are mature technologies:
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