Standard Power reduction methods

By understanding the main contributors (i.e static and dynamic) for total power consumption in the design, it's good to move ahead to understand the traditional approaches that many designers are following to reduce the total power consumption.

If we look at the process flow, the biggest opportunities for power reduction exist in pre-synthesis at the higher levels of abstraction. Since 80% or more of chip power is determined at the register transfer level (RTL) or at the architectural level, full chip analysis before synthesis can help in isolating architectural power problems that may be easily solved with RTL modifications.

Once the design is synthesized, there is much less opportunity to reduce power consumption. At the same time, accurate verification is critical at this stage to ensure that the design meets its power consumption specification.

In the recent days of advancements in technology _power consumption_ along with performance became the new metric for competitiveness in high-end SoC markets.In order to deal with power management the whole electronics community is employing various techniques for power reduction.

Managing the power early in Architectural exploration :

MAS(Micro Architecutral Specification) of RTL is the prime level to calculate the gate count in turn to determine the total power consumption of the chip.Designer should tackle power at one or more abstraction level depending on their needs and to go for refining the architecture by using additional low-power design techniques. ( Making more appropriate micro-architecture to create low power design) .

In simple words to achieve low-power targets, SoC designers must take a top-down approach beginning at the architectural level, continuing through RTL analysis and optimization, to power sign off.

One should analyze the effect on performance and the silicon area before evaluating the low power management technique during the architectural level. There are various power reduction methods that have been in use for some time and which are mature technologies:

Scope of the problem

The power consumption of a SOC design has two components: dynamic power and static power .
i.e Ptotal = Pstatic + Pdynamic;


Dynamic power is the power consumed when the device is active ,i.e. when the signals are changing their values.Static power is the power consumed when the device is powered up , but no signals are changing values and it's accounted mainly due to the leakage esp in CMOS devices.

Dynamic power (Iswitch):
It mainly has two components ; the first arises from the momentary short circuit currents called crowbar currents that flow from power to ground when the transistor stack switches it's state i.e. while the transistor's inputs change from low to high or from high to low , the p-channel and n-channel transistors are both for an instant "on" in their linear regions.

The second component is the capacitive power - the power required to charge and discharge the output capacitance on a gate

Pdyn = Load capacitance(C) * square of the supply voltage(Vdd) * frequency(f)

If the ramp time of the input signal can be made short, then the dynamic power is dominated mainly by the capacitive power
Thus if observed, due to the quadratic dependency of the power on the supply voltage , reducing the supply voltage would be the best option.But, by lowering the supply voltage we are also trying to lower the transistor output currents,lengthening the signal delays and thus degrading the performance.So in order to balance this effect the threshold voltage levels are also lowered along with the supply voltage .

Static power (Ileak):
Static power has four main sources of Leakage Currents;
Sub-Threshold leakage Current : The current that flow from drain to source when operating in weak inversion region
Gate leakage Current : The current that flows due to gate oxide tunneling and hot carrier injection
Gate Induced Drain Leakage : The current that flows from drain to substrate due to high field effect in the drain
Reverse Bias Leakage : The current due to minority carrier generation and drift in depletion regions

Among the four components, Sub-Threshold leakage forms the dominant component due to it's negative exponential dependency on threshold voltage ; i.e. as mentioned before to meet the performance and reduce dynamic power if Vt is reduced then Sub-threshold leakage increases exponentially with Vt.This trade off becomes a main point of concern while deciding the low power strategies. One of the methods proposed for decreasing the leakage current is using reverse-body bias (RBB) to increase the threshold voltage of transistors in the STANDBY state

With the shrinking technology, gate-oxide is so thin, and the gate leakage current is growing exponentially,and the use of high -K dielectric material forms the only effective way to reduce this leakage. As we move ahead towards 65nm and 45nm ; the dynamic power equals to leakage current equals to gate leakage current.
According to one of the IRTS reports,at the 65-nm node, dynamic-power density and leakage power would increase by 1.43 and 2.5 times, respectively. At the 45-nm node, the ITRS predicts, dynamic-power and leakage-power density will increase to two and 6.5 times, respectively. In reality, designs in high-speed 65-nm processes lose as much as half their power to leakage. Many in the industry believe that, by the 45-nm node, ICs will lose as much as 60% of their power to leakage.

Low Power - "Going green"

The "going green" thought is vogue in every industry,it goes from recycling paper,recycling batteries,recycling printer catridges...and many .. and finally thus bother the semiconductor industry as alot for it's contribution for the power consumption in most of the house hold and office appliances we use. Take for example our own TV sets at home , that has it's small red LED glowing, indicating the phantom power consumption in the device,even after you "power off" the system using your remote.The same goes into our standby mode of the PC.

Now, while we start dissecting deep down into each of these various devices,we then find the power consumption of each chip that gets collectively embedded into the whole device ,responsible for the phantom power of the device. It's here that we need to look that every chip that forms this device needs to have a control on the amount of power consumbed.

With the rapid progress in semiconductor technology from 130nm to 90nm to 65nm and then next to 45 nm, the chip density is increasing driving an increase in performance and has further increased the frequencies higher at the cost of power dissipation on chip (SoC) design. This penalty is making the power consumption in battery-operated portable devices a major concern as the battery life of the device is affected . The goal of low-power design for battery-powered devices is thus to extend the battery service life while meeting performance requirements.
This move for low power is a design goal not just for the portable devices ,even for non-portable devices since excessive power dissipation in these devices can result in increased packaging and cooling costs.

To combat this problem, designers are using aggressive approaches at every step of the design process, from software to architecture to implementation.

Thus, entering the blog with this introduction, we would share the various techniques that are used and can be used for conserving power in a complex SOC designs , based on few percepts of the various seminars we've attended.