Power gated controller.

In our previous discussion, we have seen that control signals are required for each power cell in a proper sequence to achieve power gated technique in the design.

During the architecture phase of the project,
Designer will make the decision on which block to shut-down and when and how long this has to be shut-down, is isolation required or not,is retention required or not if required how much state to retain during power down.

Godwin in his blog, well suggests to have a separate power gated controller block for each power domain that takes inputs from the main power control logic and generates the power down signals in the desired sequence. Few control signals required to perform the above task are,
1. Control Signal for the Power Switch (PWR_EN)
2. Control Signal for the Isolation Cell Enable (ISO_EN)
3. Control Signal for the retention flops (SAVE and RESTORE)

All the above signals need to be generated in the right order to avoid the malfunction of the circuit.
One of the sequence to follow,
To power-down the block :
1. Disable the clock
2. Generate SAVE : This will indicate that the contents of the main register in the power gated block moved into retention latch.
3. Generate ISO_EN: This will enable isolation cells to be active and clamp the output of the power gated block to either '1' or '0'.
4. Since all the basic elements are informed of the shut-down operation, now generate PWR_EN, to turn off the power rails, that control specific blocks.

To power-up the block :
1. Generate PWR_EN, to turn on the power rails, that control specific blocks.
2. Disable ISO_EN : This will disable isolation cells.Once disabled, the output of the power gated block is connected to the next power-on block.
3.Generate RESTORE : This will indicate that the the main register in the power gated block restore the data saved in retention latch.
4. Enable the clock.

Level Shifters

As discussed , as the design incorporates a mix of voltages , there is a need for a voltage translation logic that takes care of the interfaces between different voltage domains.

Practically, if looked at a signal in a 5v domain if driven by a signal from a 1v domain,it is a cause of concern as a 1v swing would not be reaching even the threshold value of the 5v swing.But,presently with the shrinking technology most of the chips have their voltages around 1v in the view of reducing dynamic power.
Then here there could be a question like, how could a signal from a 0.9v domain driving a 1v domain could pose any problem. Here the problem comes from the fact that such a 0.9v signal could make both the transistors ON thus resulting in a crowbar current(Both pmos and nmos are ON when the voltage lies between Vtn and Vdd+Vtp) .Apart from this there could also be certain timing closure problems for each voltage domain when the required voltage swings are not met.Thus it's here the solution of level shifters mitigates the problem.

The purpose of the level shifter is to convert the signal voltage to the correct voltage of the receiving domain.There are two cases :

Shifting the voltage down: This is easier than shifting the voltage high.A simple level shifter circuit of H2L type could be a simple inverter or buffer that is powered by the lower voltage domain.

Shifting the voltage high: This is complex because of the low strengths of the driving signal.The circuit is complex with usage of two power supplies from both the domains.Thus there is also a requirment of careful placement of these cells to minimize the area.

In applications where there is a mix of power gating and Multiple VDD strategies in the design there are special cells called Enable Level Shifters(ELS), that combine the isolation logic along with the level shifter fucntionality.

Retention register

As discussed earlier( post name : power gating ), When power gating is used, the system needs some form of state retention strategy to store it's internal state information.The best approach is to replace a standard register with a retention register when power gated domain is shut down. A retention register contains a shadow register that can save the register data during power down and restore it at power up.

Why only Retention register ?
Retention registers are special low leakage flip-flops used to hold the data of main register of the power gated block. These registers are always powered up. Power gating controller controls the retention mechanism such as when to save the current contents of the power gating block and when to restore it back.

Here one of the key architectural decision in power gating is how much state to retain during power down.Based on storage there are two types of retention.

1. Full state retention : Replacing all register present in the power gated block with retention register. (i.e Retaining the full state of the power gated block) during power down.
Advantage : Most robust, Verification is easy
Disadvantage : Area penalty

2. Partial state retention : Retaining some of the internal state of the block[Shallow state]is saved in the retention.But here the biggest challenge is to assure that all non retained register power up in legal, safe and variable states.

FIFOs, memories and counter are the best example where partial state retention is employed.

[Shallow state : Registers that directly control the logic of the design]
[Deep state : Registers that are used by the state machine which contain lager amount of data]

There are three types of retention.
1. Single save/restore pin retention latch (Slave latch being always on)
2. Single pin Balloon Latch.
3. Dual Pin Balloon Latch.
Figure shows a flop with retention cell(Dual pin baloon latch) along with the necessary control signals. SAVE and RESTORE.

SAVE is a control signal used to store the state of the register into retention latch.
RESTORE is a control signal used to restore the state of the register from the retention latch value.Restore operation is done irrespective of the clock.The retained value is forced into the slave latch.

When system wants turn off the power domain block following are steps to be followed in sequence :
1. Disable the clock .
2. Asserting SAVE signal before sending the turn off signal.
3. Disable the power(Vdd) to the block.

When system wants to turn on the power domain block,
1. Enable the power(Vdd) to the block.
2. Asserting RESTORE signal to retain the state of main register from retention latch.
3. Enable the clock.

Isolation Cell

As discussed earlier , with a header switch fabric, the output of the power domain block discharges towards Vss, while in case of a footer switch fabric, the output charges towards Vdd when the switch is turned off. Here there is no guarantee that the power gated output will fully discharge to ground or charge to the supply, which results in a floating output(transistors spend more in threshold results in a crowbar current) which in turn affects the behavior of the power-on block.In order to overcome this, an isolation strategy is required at the output of the power gated block.

One of the isolation strategy to combat the above effects is an isolation cell that isolates the power gated block from the power on block by clamping the output of the power gated block to a fixed value either logic '1' or logic '0' depending on the isolation control signal given by the power controller block.

Why only isolation cells ?
Isolation cells in the library are designed so that they do not experience the crowbar current when input signal floats, as long as the isolation control input is off.They are always powered on during the power down mode.

There are various combinations of gates and transistors for achieving the property of isolation.
1. AND gate function clamps the output at '0'
2. OR gate function clamps the output at '1'
3. PULL up(pmos) transistor clamps the output at '1'
4. PULL down(nmos) transitor clamps the output at '0' when it receives the isolation control signal from the power gated controller.

While the transistor approach introduces multiple drivers on the power gated net(Net becomes a shared channel) a careful sequencing is required in order to avoid this contention where testability becomes very difficult. The advantage is , it occupies less silicon area and less timing cost as compared to a gate-style isolation cell.

Power gated switches.(sleep transistor)

A sleep transistor is reffered to either PMOS or NMOS high Vth transistor that connects power to the power domain from the permanent power supply which is commonly called "virtual power supply ".
The sleep transistors are controlled by a power management unit to switch on/off power supply to the circuit.The PMOS sleep transistor is named as "Header switch" and the NMOS sleep transistor is named as "Footer switch".

Header switches turn off VDD and keep VSS on. As a result, the output of a power gated block collapse towards the ground(output capacitor discharges towards the ground) when the switch is turned off.It allows a simple design of a pull-down transistor(PMOS) to isolate power-off cells and clamp output signals in “0”.

The footer switch is used to control VSS supply. As a result the output of power gated block charge towards the supply voltage(vdd) when the switch is turned off. Designs become more sensitive to ground noise on the virtual ground (VIRTUAL_VSS) coupled through the footer switch. The isolation on “0 state becomes complex due to loss of the virtual ground in sleep mode and necessity of bypassing footer switch to reach permanent VSS.

Footer and Header sleep transistor with isolation cell.

The key issues affecting while taking the desicion are "Area, cost,IR drop constraints". The below are the few advantage/disadvantage with the Header and footer switches :
1. Footer switch occupy less silicon area relative to Header switch.
2. PMOS transistor is less leaky than NMOS transistor of a same size.
3. PMOS has lower drive current than NMOS of a same size.

Implementation of power gating in a design

The key elements required while implementing the power gating technique in the design are
1. Power gated switches.
2. Isolation cells.
3. Retention Cells.
4. Level shifter.

The entire design is divided into a number of power gated functional blocks(A collection of design elements which share the common supply), always on functional block,Power switching Fabric and Power gating controller.

Power switching network : Unlike always_on block the power gated block receives its power through power switching network.This network switches either Vdd or Vss to the power gated block.The switching fabric typically consist of large number cmos switches distributed or within the power gated block.

There are two approaches for controlling the power to the power gated domain.

1. Fine grain power gating: Fine-grain power gating encapsulates the switching transistor as a part of the standard cell logic. Here the primary burden of adding switching transistors is left with the library IP provider or standard cell designer. This means that it is possible to use a traditional design flow to deploy fine grain power gating but significantly increases the silicon area..
An example of a fine-grain power gated shown below, where we can observe power switch is connected directly to the standard cell.In order to keep the area overhead to a minimum, fine-grained power gates are implemented as footer switches to ground as NMOS transistor.

The disadvantage of the fine-grain sleep transistor is implementation adds a sleep transistor to every cell that results in significant area increase. Also, it is not able to use the normal standard cells provided by library vendors and ASIC
foundries. Another issue is that the cells become more sensitive to PVT variations, because the built-in sleep transistor is subject to PVT variation which results in added IR-drop variation inthe cell and hence performance variation.

2. Coarse grain power gating : In coarse-grain power gating, the power-gating transistor is a part of the power distribution network rather than the standard cell. One sleep transistor cell is used to turn on and off a set of standard cells(power domain function block).

The coarse-grained approach requires less area than fine-grain power gating due to the lower number of sleep transistors and less routing of enable signals for power gating. Fewer sleep transistors result in better leakage control.
The disadvantage is it might take several clock cycles to power up a larger block of logic cells.

An example of coarse grain power gating is shown below where we can see single power switch transistor is connected to the power gated logic.

The advantage of this approach is less sensitive to PVT variation and introduces less IR-drop variations than the “fine-grain” implementations. Also, the area overhead is significantly smaller as compared to fine-grain.

There are two ways of implementing a coarse-grain structure:

2.a Ring-based Network: The power switches are placed around the perimeter of the power gated block that is being switched-off as a ring.
In the ring style implementation, a virtual power ring is added to surround each power domain. The sleep transistors are placed between permanent power ring and virtual power rings to control power supply to each power domain, as shown in Fig,

It has small impact on placement and routing. However, it could result in more IR-drop at center of the design due to thelimited drive of the sleep transistors distance from the center.

2.b Grid/Column-based Network: The power gates are distributed throughout the power gated region.

In the grid style sleep transistor implementation, the sleep transistors are placed close to power grid to connect permanent power network and virtual power networks, as shown in the above Fig.

The advantages of the grid style implementation are the better IR-drop management because each sleep transistor drives local cells.

The drawback of the implementation is its impact on routing and physical synthesis, because the sleep transistors are distributed in the design area.

Here the key challenge involved with the switching fabric is to limit the in-rush current(causes voltage spikes on the supply) when the power is reconnected to power gated block to avoid the excessive IR drop in the power network.This drop in turn increases the delay in the network.It can corrupt the function as well as retention register in the power gated blocks when power is reconnected if in rush current is not controlled.

Power Gating

From the previous post we have seen few techniques to reduce the dynamic power (Clock gating,Multi Vdd) as well as static power ( Multi Vt). But that is not enough since during standby mode the design continues to consume leakage power, Now let's move on to the most robust method 'Power gating technique' the most effective method to reduce the leakage current.

Power Gating or Power switch off technique is a mechanism to turn off the blocks temporarily when it is idle/based on the requirements to reduce the static power dissipation.The turn off time can also be called as "low power mode/inactive mode" .When the blocks are turned on once again,they are called as "active mode".The strategy behind power gating is to switch these two modes at the appropriate time to reduce the power while minimizing the impact on performance.

There are two types of architectural decisions with power gating:static power gating and dynamic power gating.

In static power gating ,we try to power gate a particular block in the design based on application and this block remains ON/OFF through out the normal operation of the chip until the chip is re- initialized or re-configured through external input signals or by setting certain configuration registers in the chip or during software re-initialization. This is a simpler approach that can be used based on the application requirements where on design,implementation and verification perspective there is only a need to check that the power gated block doesn't affect the functionality of the design.

For example, it could be switching of a peripheral interface of a CPU for a particular application.

In dynamic power gating ,the decision is made on the fly while the chip is running based on various parameters decided by the power control logic of the chip .The main goal of dynamic power gating is to reduce the leakage power of the chip by defining power domains and analyzing the data paths and modes of operation of the chip while it is running.The decision making of the power control for each power domain in the design is done either by software or hardware.

In a software based approach the driver software can schedule the power down/up operations.

For example ACPI introduced for PC's gives the controllability of power controlling decisions to the operating system.

The operating system is aware of new application, and it has the data to make power-management decision.Although ACPI targets desktops ans notebooks,it makes a good model to follow when developing a software based power management system for embedded systems. With ACPI, software automatically controls the power to peripherals, ans peripherals can also activate the processor.For example ,receiving an incoming call with a modem powers the processor from standby mode in time to capture the data.

In a hardware based approach either hardware timers are utilized or a dedicated power management controller is another option that maintains the control logic to control all the power domains.

(While in the whole blog when we refer to power gating , we are mainly referring to the dynamic power gating .)

The architecture and implementation of the power gating in a design ,includes certain trade-off's and challenges respectively, they are:

Architectural trade-offs involved with this technique :

1. Power gating affects design architecture.
2. It increases time delays as power gated modes have to be safely entered and exited.
3. The possible amount of leakage power saving in such low power mode and the energy dissipation to enter and exit such mode introduces some architectural trade-offs.
4. The time and energy cost to recover the lost data when the block is re entered to active
mode.

Implementation challenges involved with power gating are,

1. Adding sleep transistor/power switches to switch off the power supplies to the idle circuit.

1.The output of a power gated design may ramp off slowly , as a result these outputs spend significant amount of time at threshold voltage,thus causing large crowbar currents in the always power on block.Isolation strategy is required to overcome this.

2. Retention strategy is required for some power gated blocks, as it is required to store the internal state of block during power down and to store this state during power up.

3. A dedicated power management controller is required for shutting down the blocks in a proper sequence.

4. It also requires a system-level understanding to decide on the addition of power gates,isolation,retention in the design and when to control them.

5. Performing power aware verification of the design is a biggest challenge.

State retention and restoration required for those power gated designs that need to resume their operations on a wake-up event based on the states information.here are three methods for the state retention and restoration methods.

1. Application software that writes specified register and memory values to disk storage before shutting down power supplies. At wakeup,the software writes the saved states back into the design.

2. State-retention and -restoration method uses a design’s scan chains to shift out register states into an always powered memory before power-down and shift-in of the states at wake-up.

"Both the above methods usually take too long to read and write which consumes a lot of power."

3. Retention register and latches that contains a shadow register that can efficiently store and restore states during power down/up.